1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically, to a semiconductor memory device internally provided with a logic circuit and a controlling method thereof.
2. Description of the Background Art
FIG. 53 is a diagram showing a pin arrangement of a conventional synchronous dynamic random access memory (SDRAM) having a capacity of 64 Mbit and a bus width of 16 bits.
FIG. 54 is a table showing terminal names and functions of the SDRAM.
Referring to FIGS. 53 and 54, the conventional SDRAM is enclosed in a package having 54 pins as terminals. The conventional SDRAM includes: a terminal CLK receiving a master clock; a terminal CKE receiving a clock enable signal; a terminal /CS receiving a chip select signal; a terminal /RAS receiving a row address strobe signal; a terminal /CAS receiving a column address strobe signal; and a terminal /WE receiving a write enable signal.
The conventional SDRAM further includes: terminals DQO to DQ15 receiving and outputting a data input/output signal; a terminal DQM (U/L) inputting/outputting an output disable signal /write mask signal; terminals A0 to A11 receiving an address; terminals BA0, BA1 receiving a bank address; a terminal VDD supplied with a power supply potential; a terminal VDDQ supplied with a power supply potential for output; a terminal VSS supplied with a ground potential; and a terminal VSSQ supplied with a ground potential for output.
As shown in FIG. 53, the pins for data input/output and power supply sources are arranged from as pins 1 to 13 and 42 to 54. The pins for control signals and clock signals are arranged as pins 15 to 19 and 37 to 39. Address input pins are arranged as pins 20 to 35. Such a terminal arrangement has generality to some extent, and is commonly used for a circuit board in a system provided with a memory.
FIG. 55 is a diagram showing a structure of a conventional DRAM provided with a logic.
Referring to FIG. 55, a chip 501 has a DRAM 504 and a logic 508, and is also provided with terminals for inputting or outputting control signals /RAS, /CAS, . . . , /CS, an address signal ADD, and a data signal DATA for accessing the DRAM.
Chip 501 further includes terminals for inputting control pins CTR0, CTR1 specific to a logic and a request signal REQ requesting the logic for access, and a terminal for outputting a strobe signal STRB used by the logic to notify an external portion of completion of a process.
Conventionally, for controlling logic 508, a special pin has been arranged. Thus, a greater number of pins are required for a general purpose DRAM as shown in FIG. 53, or a controller for controlling the DRAM with a logic must be prepared to form a system on a board. As a result, generality for connection to a general microcomputer is impaired, or a special command for the microcomputer must be used to control the system.